19 search results - page 1 / 4 » Sensitivity Analysis of a Cluster-Based Interconnect Model f... |
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
An efficient model-order reduction technique for general RLC networks is proposed. The method is extended from the previous projection-base moment matching method with considerin...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
This paper presents a revised model for the yield analysis of FPGA interconnect layers. Based on proven yield models, this work improves the predictions and assumptions of previous...