13 search results - page 2 / 3 » Signal Integrity: Fault Modeling and Testing in High-Speed S... |
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
ATS
2009
IEEE
13 years 10 months ago
2009
IEEE
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
ICCD
2003
IEEE
13 years 10 months ago
2003
IEEE
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
VLSID
2000
IEEE
13 years 9 months ago
2000
IEEE
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
GLVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...