109 search results - page 3 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
CF
2007
ACM
13 years 10 months ago
2007
ACM
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
CAINE
2003
13 years 7 months ago
2003
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
ISCA
1996
IEEE
13 years 10 months ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
EUROPAR
2005
Springer
13 years 11 months ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...