20 search results - page 4 / 4 » Simultaneous Gate Sizing and Fanout Optimization |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run...
TCAD
2008
13 years 4 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
DAC
2009
ACM
13 years 9 months ago
2009
ACM
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...