27 search results - page 3 / 6 » Simultaneous Timing Driven Clustering and Placement for FPGA... |
FPGA
1999
ACM
13 years 10 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
TCAD
2008
13 years 5 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
GLVLSI
2007
IEEE
14 years 3 days ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...