17 search results - page 2 / 4 » Simultaneous Wire Sizing and Wire Spacing in Post-Layout Per... |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
TCAD
2008
13 years 4 months ago
2008
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...