36 search results - page 1 / 8 » Soft Error Rates with Inertial and Logical Masking |
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
DSN
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
ISQED
2010
IEEE
13 years 10 months ago
2010
IEEE
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...