36 search results - page 3 / 8 » Soft Error Rates with Inertial and Logical Masking |
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
PATMOS
2007
Springer
14 years 4 days ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
ISQED
2006
IEEE
14 years 1 days ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
TCAD
2008
13 years 6 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...