35 search results - page 2 / 7 » Soft Error-Aware Power Optimization Using Gate Sizing |
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...