33 search results - page 2 / 7 » Software-Based Delay Fault Testing of Processor Cores |
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
MTV
2005
IEEE
13 years 10 months ago
2005
IEEE
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time...
DFT
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
CSREAESA
2009
13 years 6 months ago
2009
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...