10 search results - page 2 / 2 » Split-Row: A Reduced Complexity, High Throughput LDPC Decode... |
DATE
2009
IEEE
14 years 15 days ago
2009
IEEE
Abstract—In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-ChaudhuriH...
ICC
2008
IEEE
14 years 6 days ago
2008
IEEE
Abstract— The design of LDPC decoders with low complexity, high throughput, and good performance is a critical task. A well-known strategy is to design structured codes such as q...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
ISVLSI
2005
IEEE
13 years 11 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
ADT
2005
13 years 5 months ago
2005
: The main problem concerning the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this proble...