The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
Carlo Brandolese, Fabio Salice, William Fornaciari...
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...