Static power modeling of 32-bit microprocessors

The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level power model is founded on a functional decomposition of the activities accomplished by a generic microprocessor. The proposed model has significant generalization capabilities. It allows estimation of the power figures of the entire instruction-set starting from the analysis of a subset, as well as to power characterize new processors by using the model obtained by considering other microprocessors. The model is formally presented and justified and its actual application over five commercial microprocessors is included.This static characterization is the basic information for system-level power modelling of hardware/software architectures. Keywords-- Power Modelling and Estimation, Low-power design, Embedded systems, Modelling, Estimation

• Type: Journal
• Year: 2002
• Where: TCAD
• Authors: Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto
• Keywords: Microprocessors, Model, Modelling, TCAD 2002