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ICCAD
2003
IEEE
379views Hardware» more  ICCAD 2003»
14 years 2 months ago
A Statistical Gate-Delay Model Considering Intra-Gate Variability
This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly i...
Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
13 years 11 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
14 years 17 days ago
On hierarchical statistical static timing analysis
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
Bing Li, Ning Chen, Manuel Schmidt, Walter Schneid...
VTS
2003
IEEE
89views Hardware» more  VTS 2003»
13 years 11 months ago
Diagnosis of Delay Defects Using Statistical Timing Models
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
ASPDAC
2006
ACM
230views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Statistical Bellman-Ford algorithm with an application to retiming
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Li...