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» Statistical Power Estimation for FPGA
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FPL
2005
Springer
115views Hardware» more  FPL 2005»
13 years 10 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 1 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
IPPS
2006
IEEE
13 years 11 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
FPL
2008
Springer
98views Hardware» more  FPL 2008»
13 years 6 months ago
Rapid estimation of power consumption for hybrid FPGAs
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of ...
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Ste...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
13 years 10 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan