246 search results - page 2 / 50 » Statistical gate sizing for timing yield optimization |
TVLSI
2008
13 years 5 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...