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ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
13 years 10 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
CODES
2006
IEEE
13 years 11 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
IEEEPACT
2008
IEEE
14 years 4 days ago
Multi-mode energy management for multi-tier server clusters
This paper presents an energy management policy for reconfigurable clusters running a multi-tier application, exploiting DVS together with multiple sleep states. We develop a the...
Tibor Horvath, Kevin Skadron
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
13 years 11 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
ISCAS
2006
IEEE
154views Hardware» more  ISCAS 2006»
13 years 11 months ago
A novel Fisher discriminant for biometrics recognition: 2DPCA plus 2DFLD
— this paper presents a novel image feature extraction and recognition method two dimensional linear discriminant analysis (2DLDA) in a much smaller subspace. Image representatio...
R. M. Mutelo, Li Chin Khor, Wai Lok Woo, Satnam Si...