82 search results - page 1 / 17 » Synthesis of High Performance Low Power Dynamic CMOS Circuit... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
TVLSI
2010
12 years 11 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...