61 search results - page 2 / 13 » Synthesis of Selectively Clocked Skewed Logic Circuits |
ICCD
2000
IEEE
13 years 10 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
GLVLSI
2010
IEEE
13 years 11 months ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
ISPD
2010
ACM
14 years 19 days ago
2010
ACM
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...