18 search results - page 3 / 4 » Systolic Algorithm Mapping for Coarse Grained Reconfigurable... |
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
CASES
2008
ACM
13 years 7 months ago
2008
ACM
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
TVLSI
2008
13 years 5 months ago
2008
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...