61 search results - page 1 / 13 » Test Pattern Generation Under Low Power Constraints |
EVOW
1999
Springer
13 years 9 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initiali...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
TC
2008
13 years 4 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
ATS
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...