203 search results - page 2 / 41 » Test Pattern Generator for Delay Faults |
DAC
2005
ACM
13 years 7 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
DDECS
2007
IEEE
13 years 9 months ago
2007
IEEE
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
VTS
2008
IEEE
13 years 11 months ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...