193 search results - page 2 / 39 » The TigerSHARC DSP Architecture |
DAC
1991
ACM
13 years 9 months ago
1991
ACM
ISSS
1995
IEEE
13 years 9 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
ISSS
1996
IEEE
13 years 10 months ago
1996
IEEE
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
ISCAPDCS
2001
13 years 7 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
IPPS
1998
IEEE
13 years 10 months ago
1998
IEEE
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...