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» Timing Analysis with Implicitly Specified False Paths
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ASPDAC
2006
ACM
125views Hardware» more  ASPDAC 2006»
13 years 8 months ago
Efficient identification of multi-cycle false path
Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...
Kai Yang, Kwang-Ting Cheng
ICCAD
1999
IEEE
66views Hardware» more  ICCAD 1999»
13 years 9 months ago
Timing-safe false path removal for combinational modules
A delay abstraction of a combinational module is a compact representation of the delay information of the module, which carries effective pin-to-pin delay for each primary-input/pr...
Yuji Kukimoto, Robert K. Brayton
DATE
2004
IEEE
142views Hardware» more  DATE 2004»
13 years 8 months ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
13 years 8 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
DAC
1995
ACM
13 years 8 months ago
Performance Analysis of Embedded Software Using Implicit Path Enumeration
—Embedded computer systems are characterized by the presence of a processor running application-specific dedicated software. A large number of these systems must satisfy real-ti...
Yau-Tsun Steven Li, Sharad Malik