15 search results - page 3 / 3 » Timing-reasoning-based delay fault diagnosis |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper proposes an all digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers,...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Faster defect localization is achieved by combining IC simulations and internal measurements. Time resolved photon emission records photons emitted during commutations (current) r...
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper prese...
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ASAP
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...