3 search results - page 1 / 1 » Transistor and Pin Reordering for Gate Oxide Leakage Reducti... |
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...