18 search results - page 1 / 4 » Transistor reordering rules for power reduction in CMOS gate... |
ASPDAC
1995
ACM
13 years 8 months ago
1995
ACM
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
ICCAD
2005
IEEE
13 years 10 months ago
2005
IEEE
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...