65 search results - page 3 / 13 » Unified decoder architecture for LDPC turbo codes |
ICIP
2005
IEEE
14 years 7 months ago
2005
IEEE
In distributed video source coding side-information at the decoder is generated as a temporal prediction based on previous frames. This creates a virtual dependency channel betwee...
TVLSI
2008
13 years 5 months ago
2008
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
ISCAS
2008
IEEE
13 years 12 months ago
2008
IEEE
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
SIPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
JSAC
2008
13 years 5 months ago
2008
Abstract-- We explore the performance and hardware complexity tradeoffs associated with performing iterative multipleinput multiple-output (MIMO) detection using a sphere decoder a...