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» Use of Multiple IDDQ Test Metrics for Outlier Identification
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VTS
2003
IEEE
88views Hardware» more  VTS 2003»
13 years 10 months ago
Use of Multiple IDDQ Test Metrics for Outlier Identification
With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for IDDQ test due to ...
Sagar S. Sabade, D. M. H. Walker
VLSID
2003
IEEE
145views VLSI» more  VLSID 2003»
14 years 5 months ago
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
Increasing values and spread in leakage current makes it impossible to distinguish between faulty and fault-free chips using single threshold method. Neighboring chips on a wafer ...
Sagar S. Sabade, D. M. H. Walker
VTS
2006
IEEE
118views Hardware» more  VTS 2006»
13 years 10 months ago
X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data
A statistical technique X-IDDQ for extracting defect information from IDDQ data is presented that is effective for detection of defects in ICs. The technique treats the IDDQ measu...
Ashutosh Sharma, Anura P. Jayasumana, Yashwant K. ...
DFT
2002
IEEE
115views VLSI» more  DFT 2002»
13 years 9 months ago
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis
IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio o...
Sagar S. Sabade, D. M. H. Walker
DFT
2003
IEEE
86views VLSI» more  DFT 2003»
13 years 10 months ago
CROWNE: Current Ratio Outliers with Neighbor Estimator
Increased leakage and process variations make distinction between fault-free and faulty chips by IDDQ test difficult. Earlier the concept of Current Ratios (CR) was proposed to sc...
Sagar S. Sabade, D. M. H. Walker