6 search results - page 1 / 2 » Weak Write Test Mode: An SRAM Cell Stability Design for Test... |
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Tes...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
DFT
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...