Sciweavers

15 search results - page 2 / 3
» When FPGAs are better at floating-point than microprocessors
Sort
View
TVLSI
2010
13 years 13 days ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
13 years 11 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
14 years 12 days ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
MICRO
1994
IEEE
124views Hardware» more  MICRO 1994»
13 years 10 months ago
A comparison of two pipeline organizations
We examine two pipeline structures which are employed in commercial microprocessors. The first is the load-use interlock (LUI) pipeline, which employs an interlock to ensure corre...
Michael Golden, Trevor N. Mudge
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 9 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun