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FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
13 years 6 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
13 years 6 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
FPL
2008
Springer
98views Hardware» more  FPL 2008»
13 years 6 months ago
Rapid estimation of power consumption for hybrid FPGAs
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of ...
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Ste...
FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
13 years 6 months ago
When FPGAs are better at floating-point than microprocessors
It has been shown that FPGAs could outperform high-end microprocessors on floating-point computations thanks to massive parallelism. However, most previous studies re-implement in...
Florent de Dinechin, Jérémie Detrey,...
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
13 years 6 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston