This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
— The high-order compact finite difference (HCFD) method is adapted for interconnect modeling. Based on the compact finite difference method, the HCFD method employs the Chebys...
The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach tran...
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, ...