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GLVLSI
2002
IEEE
123views VLSI» more  GLVLSI 2002»
13 years 10 months ago
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU
Joel Grodstein, Rachid Rayess, Tad Truex, Linda Sh...
GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
13 years 10 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
GLVLSI
2002
IEEE
98views VLSI» more  GLVLSI 2002»
13 years 10 months ago
Minimizing concurrent test time in SoC's by balancing resource usage
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
GLVLSI
2002
IEEE
118views VLSI» more  GLVLSI 2002»
13 years 10 months ago
Novel interconnect modeling by using high-order compact finite difference methods
— The high-order compact finite difference (HCFD) method is adapted for interconnect modeling. Based on the compact finite difference method, the HCFD method employs the Chebys...
Qinwei Xu, Pinaki Mazumder
GLVLSI
2002
IEEE
105views VLSI» more  GLVLSI 2002»
13 years 10 months ago
Board-level multiterminal net assignment
The paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in Clos-Folded FPGA based logic emulation systems. The approach tran...
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, ...