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ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
13 years 11 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
13 years 11 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
13 years 11 months ago
Transition time bounded low-power clock tree construction
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...
Min Pan, Chris C. N. Chu, J. Morris Chang
ISCAS
2005
IEEE
105views Hardware» more  ISCAS 2005»
13 years 11 months ago
Low-sensitivity current-mode active-RC filters using impedance tapering
—This paper is concerned with a new design method of low-sensitivity current-mode filters, which results from lowsensitivity voltage-mode filter design using impedance tapering. ...
Drazen Jurisic, Neven Mijat, George S. Moschytz
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...