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VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
14 years 5 months ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 5 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
VLSID
2005
IEEE
82views VLSI» more  VLSID 2005»
14 years 5 months ago
Dual-Edge Triggered Static Pulsed Flip-Flops
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
Aliakbar Ghadiri, Hamid Mahmoodi-Meimand
VLSID
2005
IEEE
223views VLSI» more  VLSID 2005»
14 years 5 months ago
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee...
VLSID
2005
IEEE
129views VLSI» more  VLSID 2005»
14 years 5 months ago
A RISC Hardware Platform for Low Power Java
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
Paul Capewell, Ian Watson
VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 5 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
14 years 5 months ago
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system compon...
Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim,...
VLSID
2005
IEEE
149views VLSI» more  VLSID 2005»
14 years 5 months ago
ADOPT: An Approach to Activity Based Delay Optimization
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M....
VLSID
2005
IEEE
123views VLSI» more  VLSID 2005»
14 years 5 months ago
Variance Reduction in Monte Carlo Capacitance Extraction
In this article we address efficiency issues in implementation of Monte Carlo algorithm for 3D capacitance extraction. Error bounds in statistical capacitance estimation are discus...
Shabbir H. Batterywala, Madhav P. Desai
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 5 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...