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VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
14 years 5 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 5 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
VLSID
2007
IEEE
209views VLSI» more  VLSID 2007»
14 years 5 months ago
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
Saraju P. Mohanty, Elias Kougianos
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 5 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 5 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
VLSID
2007
IEEE
94views VLSI» more  VLSID 2007»
14 years 5 months ago
A Reduced Complexity Algorithm for Minimizing N-Detect Tests
? We give a new recursive rounding linear programming (LP) solution to the problem of N-detect test minimzation. This is a polynomialtime solution that closely approximates the exa...
Kalyana R. Kantipudi, Vishwani D. Agrawal
VLSID
2007
IEEE
98views VLSI» more  VLSID 2007»
14 years 5 months ago
Power Reduction in VLIW Processor with Compiler Driven Bypass Network
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
14 years 5 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 5 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
VLSID
2007
IEEE
128views VLSI» more  VLSID 2007»
14 years 5 months ago
A Low Power Frequency Multiplication Technique for ZigBee Transciever
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj...