Sciweavers

VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 5 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
VLSID
2008
IEEE
83views VLSI» more  VLSID 2008»
14 years 5 months ago
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
We present a discrete-time time-domain vector fitting algorithm, called TD-VFz, for rational function macromodeling of port-to-port responses with discrete time-sampled data. The ...
Chi-Un Lei, Ngai Wong
VLSID
2008
IEEE
95views VLSI» more  VLSID 2008»
14 years 5 months ago
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long cha...
Biswajit Ray, Santanu Mahapatra
VLSID
2008
IEEE
120views VLSI» more  VLSID 2008»
14 years 5 months ago
Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
Real-time embedded systems increasingly rely on dynamic power management to balance between power and performance goals. In this paper, we present a technique for continuous frequ...
Hwisung Jung, Massoud Pedram
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 5 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 5 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
VLSID
2008
IEEE
153views VLSI» more  VLSID 2008»
14 years 5 months ago
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. Howeve...
Yuanlin Lu, Vishwani D. Agrawal
HPCA
2009
IEEE
14 years 5 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
HPCA
2009
IEEE
14 years 5 months ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
HPCA
2009
IEEE
14 years 5 months ago
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
Samantika Subramaniam, Anne Bracy, Hong Wang 0003,...