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FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
13 years 8 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
FPGA
2006
ACM
100views FPGA» more  FPGA 2006»
13 years 8 months ago
A generic lookup cache architecture for network processing applications
Abstract-- In this paper, we introduce a novel architecture for constructing caches for lookup operations that are used in a variety of network processing applications. The disting...
Janardhan Singaraju, John A. Chandy
FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
13 years 8 months ago
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic
Abstract-- Increasing device densities allow chip manufacturers to integrate more functionality onto a single piece of silicon. FPGA manufacturers, such as Xilinx and Altera, use t...
Joshua Noseworthy, Miriam Leeser
FPGA
2006
ACM
156views FPGA» more  FPGA 2006»
13 years 8 months ago
A reconfigurable architecture for network intrusion detection using principal component analysis
In this paper, we develop an architecture for principal component analysis (PCA) to be used as an outlier detection method for high-speed network intrusion detection systems (NIDS...
David T. Nguyen, Gokhan Memik, Alok N. Choudhary
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
13 years 8 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
FPGA
2006
ACM
139views FPGA» more  FPGA 2006»
13 years 8 months ago
Fast and accurate resource estimation of automatically generated custom DFT IP cores
This paper presents an equation-based resource utilization model for automatically generated discrete Fourier transform (DFT) soft core IPs. The parameterized DFT IP generator all...
Peter A. Milder, Mohammad Ahmad, James C. Hoe, Mar...
FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
13 years 8 months ago
A reconfigurable hardware based embedded scheduler for buffered crossbar switches
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassil...
FPGA
2006
ACM
116views FPGA» more  FPGA 2006»
13 years 8 months ago
Performance benefits of monolithically stacked 3D-FPGA
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wo...
FPGA
2006
ACM
90views FPGA» more  FPGA 2006»
13 years 8 months ago
Improving performance and robustness of domain-specific CPLDs
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
13 years 8 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton