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ASPDAC
2001
ACM
75views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Integrated power supply planning and floorplanning
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz...
ASPDAC
2001
ACM
159views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Design and implementation of JPEG encoder IP core
Chung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yu...
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
ASPDAC
2001
ACM
59views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Module placement with boundary constraints using the sequence-pair representation
Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C....
ASPDAC
2001
ACM
102views Hardware» more  ASPDAC 2001»
13 years 8 months ago
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout
Abstract-- We describe new graph bipartization algorithms for layout modification and phase assignment of bright-field alternating phaseshifting masks (AltPSM) [25]. The problem of...
Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovs...
ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Reusable embedded in-circuit emulator
In this paper, we o introduce the Reusable Embedded In-Circuit Emulator (EICE) and Reusable EICE development system. The main function in EICE we design are testing and debugging. ...
Ing-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao
ASPDAC
2001
ACM
94views Hardware» more  ASPDAC 2001»
13 years 8 months ago
On speeding up extended finite state machines using catalyst circuitry
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical...
Shi-Yu Huang
ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
13 years 8 months ago
Towards the logic defect diagnosis for partial-scan designs
Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the la...
Shi-Yu Huang
ASPDAC
2001
ACM
78views Hardware» more  ASPDAC 2001»
13 years 8 months ago
A new congestion-driven placement algorithm based on cell inflation
Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Wei...