Sciweavers

ISCA
2002
IEEE
159views Hardware» more  ISCA 2002»
13 years 9 months ago
Avoiding Initialization Misses to the Heap
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black
ISCA
2002
IEEE
68views Hardware» more  ISCA 2002»
13 years 9 months ago
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
ICPADS
2002
IEEE
13 years 9 months ago
Evaluating and Improving Performance of Multimedia Applications on Simultaneous Multi-Threading
This paper presents the study and results of running several core multimedia applications on a simultaneous multithreading (SMT) architecture, including some detailed analysis ran...
Yen-Kuang Chen, Eric Debes, Rainer Lienhart, Matth...
ICDCS
2002
IEEE
13 years 9 months ago
A New Document Placement Scheme for Cooperative Caching on the Internet
Most existing work on cooperative caching has been focused on serving misses collaboratively. Very few have studied the effect of cooperation on document placement schemes and its...
Lakshmish Ramaswamy, Ling Liu
ICDCS
2002
IEEE
13 years 9 months ago
Group-Based Management of Distributed File Caches
We describe how to manage distributed file system caches based upon groups of files that are accessed together. We use file access patterns to automatically construct dynamic g...
Ahmed Amer, Darrell D. E. Long, Randal C. Burns
ASAP
2002
IEEE
85views Hardware» more  ASAP 2002»
13 years 9 months ago
Predictable Instruction Caching for Media Processors
The determinism of instruction cache performance can be considered a major problem in multi-media devices which hope to maximise their quality of service. If instructions are evic...
James Irwin, David May, Henk L. Muller, Dan Page
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
13 years 10 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
13 years 10 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
ICS
2003
Tsinghua U.
13 years 10 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
HUMAN
2003
Springer
13 years 10 months ago
DOC: A Distributed Object Caching System for Information Infrastructure
Object caching is a desirable feature to improve the both scalability and performance of distributed application systems for information infrastructure, the information management ...
Taehee Lee, Junho Shim, Sang-goo Lee