DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
ICS
2009
Tsinghua U.
13 years 11 months ago
2009
Tsinghua U.
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...
SC
2009
ACM
13 years 11 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
SC
2009
ACM
13 years 11 months ago
2009
ACM
The management of shared caches in multicore processors is a critical and challenging task. Many hardware and OS-based methods have been proposed. However, they may be hardly adop...
ISPASS
2010
IEEE
13 years 11 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...