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ERSA
2009
149views Hardware» more  ERSA 2009»
9 years 8 months ago
Harnessing Human Computation Cycles for the FPGA Placement Problem
Harnessing human computation is an approach to find problem solutions. In this paper, we investigate harnessing this human computation for a Field Programmable Gate Array (FPGA) p...
Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit S...
TSMC
2002
91views more  TSMC 2002»
9 years 10 months ago
On the sure criticality of tasks in activity networks with imprecise durations
Abstract--The notion of the necessary criticality (both with respect to path and to activity) of a network with imprecisely defined (by means of intervals or fuzzy intervals) activ...
Stefan Chanas, Didier Dubois, Pawel Zielinski
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
10 years 19 days ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
ICC
2007
IEEE
162views Communications» more  ICC 2007»
10 years 2 months ago
LSP and Back Up Path Setup in MPLS Networks Based on Path Criticality Index
This paper reports on a promising approach for solving problems found when Multi Protocol Label Switching (MPLS), soon to be a dominant protocol, is used in core network systems. D...
Ali Tizghadam, Alberto Leon-Garcia
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
10 years 2 months ago
Concurrent logic restructuring and placement for timing closure
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...
Jinan Lou, Wei Chen, Massoud Pedram
ICCAD
1999
IEEE
153views Hardware» more  ICCAD 1999»
10 years 2 months ago
Cycle time and slack optimization for VLSI-chips
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
Christoph Albrecht, Bernhard Korte, Jürgen Sc...
ICCAD
2000
IEEE
74views Hardware» more  ICCAD 2000»
10 years 3 months ago
Simultaneous Gate Sizing and Fanout Optimization
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
10 years 3 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
ASPDAC
2009
ACM
92views Hardware» more  ASPDAC 2009»
10 years 5 months ago
Hybrid LZA: a near optimal implementation of the leading zero anticipator
The Leading Zero Anticipator (LZA) is one of the main components used in floating point addition. It tends to be on the critical path, so it has attracted the attention of many r...
Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ien...
DAC
2008
ACM
10 years 11 months ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
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