Sciweavers

DATE
2004
IEEE
129views Hardware» more  DATE 2004»
13 years 8 months ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
13 years 8 months ago
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding
In this paper, we explore the requirements of emerging complex SoC's and describe StepNP, an experimental flexible, multi-processor SoC platform targeted towards communicatio...
Pierre G. Paulin, Chuck Pilkington, Essaid Bensoud...
DATE
2004
IEEE
80views Hardware» more  DATE 2004»
13 years 8 months ago
Random Jitter Extraction Technique in a Multi-Gigahertz Signal
In this paper, we propose a simple technique for estimating the standard deviation of a Gaussian random jitter component in a multi-gigahertz signal. This method may utilize exist...
Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-...
DATE
2004
IEEE
128views Hardware» more  DATE 2004»
13 years 8 months ago
Synthesis for Manufacturability: A Sanity Check
As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synt...
Alessandra Nardi, Alberto L. Sangiovanni-Vincentel...
DATE
2004
IEEE
151views Hardware» more  DATE 2004»
13 years 8 months ago
Dynamic Voltage and Cache Reconfiguration for Low Power
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
André C. Nácul, Tony Givargis
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 8 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
DATE
2004
IEEE
117views Hardware» more  DATE 2004»
13 years 8 months ago
Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks
We lay a foundation for modeling and validation of asynchronous designs in a multi-clock synchronous programming model. This allows us to study properties of globally asynchronous...
Mohammad Reza Mousavi, Paul Le Guernic, Jean-Pierr...
DATE
2004
IEEE
159views Hardware» more  DATE 2004»
13 years 8 months ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
DATE
2004
IEEE
174views Hardware» more  DATE 2004»
13 years 8 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt
DATE
2004
IEEE
119views Hardware» more  DATE 2004»
13 years 8 months ago
Net and Pin Distribution for 3D Package Global Routing
In this paper, we study the net and pin distribution problem for global routing targeting three dimensional packaging layout via System-on-Package (SOP). The routing environment f...
Jacob R. Minz, Mohit Pathak, Sung Kyu Lim