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DATE
2004
IEEE
135views Hardware» more  DATE 2004»
13 years 8 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
13 years 8 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
13 years 8 months ago
Workload Characterization Model for Tasks with Variable Execution Demand
The analysis of real-time properties of an embedded system usually relies on the worst-case execution times (WCET) of the tasks to be executed. In contrast to that, in real world ...
Alexander Maxiaguine, Simon Künzli, Lothar Th...
DATE
2004
IEEE
118views Hardware» more  DATE 2004»
13 years 8 months ago
Distributed Multimedia System Design: A Holistic Perspective
Multimedia systems play a central part in many human activities. Due to the significant advances in the VLSI technology, there is an increasing demand for portable multimedia appl...
Radu Marculescu, Massoud Pedram, Jörg Henkel
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
13 years 8 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 8 months ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
DATE
2004
IEEE
128views Hardware» more  DATE 2004»
13 years 8 months ago
An Assembler Driven Verification Methodology (ADVM)
This paper presents an overview of an assembler driven verification methodology (ADVM) that was created and implemented for a chip card project at Infineon Technologies AG [2]. Th...
John S. MacBeth, Dietmar Heinz, Ken Gray
DATE
2004
IEEE
157views Hardware» more  DATE 2004»
13 years 8 months ago
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning
In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently p...
Roman L. Lysecky, Frank Vahid
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
13 years 8 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
13 years 8 months ago
Analyzing On-Chip Communication in a MPSoC Environment
This work focuses on communication architecture analysis for multi-processor Systems-on-Chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-proc...
Mirko Loghi, Federico Angiolini, Davide Bertozzi, ...