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ICCAD
2007
IEEE
132views Hardware» more  ICCAD 2007»
9 years 11 months ago
Principle Hessian direction based parameter reduction with process variation
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
ICCAD
2007
IEEE
118views Hardware» more  ICCAD 2007»
9 years 11 months ago
Timing variation-aware high-level synthesis
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
Jongyoon Jung, Taewhan Kim
ICCAD
2007
IEEE
161views Hardware» more  ICCAD 2007»
9 years 11 months ago
Clustering based pruning for statistical criticality computation under process variations
— We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for critica...
Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar,...
ICCAD
2007
IEEE
101views Hardware» more  ICCAD 2007»
9 years 11 months ago
A novel SoC design methodology combining adaptive software and reconfigurable hardware
Marco D. Santambrogio, Seda Ogrenci Memik, Vincenz...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
9 years 11 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
9 years 11 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCAD
2007
IEEE
158views Hardware» more  ICCAD 2007»
9 years 11 months ago
Strategies for improving the parametric yield and profits of 3D ICs
Cesare Ferri, Sherief Reda, R. Iris Bahar
ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
9 years 11 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
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