ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper proposes a Layered Model for boundaryscan testing to help identify opportunities for standardization. Serial Vector Format [1] and an accompanying Application Programmi...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
The P1149.4 mixed-signal boundary scan standard is demonstrated with a CMOS integrated circuit. Design issues and characterization data are presented.
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
