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CAL
2002
9 years 10 months ago
Implementing Decay Techniques using 4T Quasi-Static Memory Cells
Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin...
TVLSI
2008
197views more  TVLSI 2008»
9 years 10 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
PACS
2000
Springer
121views Hardware» more  PACS 2000»
10 years 2 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
10 years 4 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
ISCAS
2008
IEEE
265views Hardware» more  ISCAS 2008»
10 years 5 months ago
Dynamic voltage and frequency scaling circuits with two supply voltages
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
Wayne H. Cheng, Bevan M. Baas
CODES
2008
IEEE
10 years 5 months ago
System-level mitigation of WID leakage power variability using body-bias islands
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ...
Siddharth Garg, Diana Marculescu
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
10 years 7 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
HPCA
2005
IEEE
10 years 11 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
10 years 11 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
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