Sciweavers

ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
13 years 11 months ago
Low-power hybrid turbo decoding based on reverse calculation
—As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper...
Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park
IPPS
2006
IEEE
13 years 11 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
IPPS
2006
IEEE
13 years 11 months ago
Power consumption comparison for regular wireless topologies using fault-tolerant beacon vector routing
Fault-tolerant Beacon Vector Routing (FBVR) is an efficient technique for routing in the presence of node failures. Several common wireless topologies exist that can be used with...
Luke Demoracski, Dimiter R. Avresky
IPPS
2006
IEEE
13 years 11 months ago
Online strategies for high-performance power-aware thread execution on emerging multiprocessors
Granularity control is an effective means for trading power consumption with performance on dense shared memory multiprocessors, such as multi-SMT and multi-CMP systems. In this p...
Matthew Curtis-Maury, James Dzierwa, Christos D. A...
IPPS
2006
IEEE
13 years 11 months ago
Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications
Recently, under a fixed power budget, asymmetric multiprocessors (AMP) have been proposed to improve the performance of multi-threaded applications compared to symmetric multiproc...
Ryan E. Grant, Ahmad Afsahi
INFOCOM
2006
IEEE
13 years 11 months ago
Optimal Power Allocation in Wireless Networks with Transmitter-Receiver Power Tradeoffs
— For many wireless communication links, such as those employing turbo codes or sequentially-decoded convolutional codes, the power consumption of the decoder at the receiver dep...
Sudarshan Vasudevan, Chun Zhang, Dennis Goeckel, D...
DSD
2006
IEEE
107views Hardware» more  DSD 2006»
13 years 11 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
DATE
2006
IEEE
122views Hardware» more  DATE 2006»
13 years 11 months ago
Power analysis of mobile 3D graphics
— The world of 3D graphics, until recently restricted to high-end workstations and game consoles, is rapidly expanding into the domain of mobile platforms such as cellular phones...
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
13 years 11 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
CODES
2006
IEEE
13 years 11 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha