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TCAD
2008
49views more  TCAD 2008»
9 years 3 months ago
Register File Power Reduction Using Bypass Sensitive Compiler
This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register f...
Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, ...
TCAD
2008
99views more  TCAD 2008»
9 years 3 months ago
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few...
TCAD
2008
82views more  TCAD 2008»
9 years 3 months ago
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
ion for Asynchronous Design Verification Hao Zheng, Member, IEEE, Jared Ahrens, Tian Xia, Member, IEEE This paper presents a compositional method with preserving abstraction for sc...
Hao Zheng, Jared Ahrens, Tian Xia
TCAD
2008
88views more  TCAD 2008»
9 years 3 months ago
Self-Adaptive Data Caches for Soft-Error Reliability
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
TCAD
2008
115views more  TCAD 2008»
9 years 3 months ago
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
Javid Jaffari, Mohab Anis
TCAD
2008
181views more  TCAD 2008»
9 years 3 months ago
A Survey of Automated Techniques for Formal Software Verification
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
Vijay D'Silva, Daniel Kroening, Georg Weissenbache...
TCAD
2008
55views more  TCAD 2008»
9 years 3 months ago
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process
Abstract--This paper presents a multiparameter momentmatching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi proc...
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
TCAD
2008
106views more  TCAD 2008»
9 years 3 months ago
Track Routing and Optimization for Yield
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
TCAD
2008
59views more  TCAD 2008»
9 years 3 months ago
Dual-Vdd Buffer Insertion for Power Reduction
King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Z...
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