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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    15 years 9 months ago
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    Download  dropzone.tamu.edu
    Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
    Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
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    ASPDAC
    2008
    ACM
    85views Hardware» more  ASPDAC 2008»
    ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip
    15 years 9 months ago
    ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip
    Download  www.engr.colostate.edu
    Abstract
    Sudeep Pasricha, Nikil Dutt
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    ASPDAC
    2008
    ACM
    174views Hardware» more  ASPDAC 2008»
    Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
    15 years 9 months ago
    Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
    Download  www.cecs.uci.edu
    In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
    Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
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    ASPDAC
    2008
    ACM
    97views Hardware» more  ASPDAC 2008»
    A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
    15 years 9 months ago
    A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
    Download  www.ics.uci.edu
    Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
    Aviral Shrivastava, Ilya Issenin, Nikil Dutt
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    ASPDAC
    2008
    ACM
    74views Hardware» more  ASPDAC 2008»
    Large-scale fixed-outline floorplanning design using convex optimization techniques
    15 years 9 months ago
    Large-scale fixed-outline floorplanning design using convex optimization techniques
    Download  orion.math.uwaterloo.ca
    A two-stage optimization methodology is proposed to solve the fixed-outline floorplanning problem that is a global optimization problem for wirelength minimization. In the first st...
    Chaomin Luo, Miguel F. Anjos, Anthony Vannelli
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